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Project Proposal-

Because of their excellent error –correcting code , low –density parity check (LDPC) codes have become very popular in telecommunication field .In this project we are interested in the hardware implementation of LDPC decoder . According to the algorithm , large number of computation have been done using variable & check node components , so we need to store a large quantity of data . As total system throughput & power consumption are also depend on memory access time & power consumed by memory block, so in our project emphasis is given to design a low power fast accessible memory. In this project, we will be designing 256 byte dual port SRAM memory architecture.

In our algorithm, computations are done using Φ(x) (= - log (tanh (1/2x)) function. Because of the complexity of the function, it is very critical to design architectural block to compute the phi value for different x values. In this project, we will also be implementing Look up table (LUT) to store the Φ(x) value for different x values , which will be directly accessed for the computation .

Group Members -

Abhijit Sil

Yasser  Ismail

Pulak Ranjan De

Project Supervisors -

Li Yijun

Abu Baker

Project Co-supervisor-

Soumik Ghosh